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pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt product data sheet supersedes data of 2002 jul 26 2004 sep 30 integrated circuits
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2 2004 sep 30 features ? operating power supply voltage range of 2.3 to 5.5 v ? 5 v tolerant i/os ? polarity inversion register ? active-low interrupt output ? low stand-by current ? noise filter on scl/sda inputs ? no glitch on power-up ? internal power-on reset ? 8 i/o pins which default to 8 inputs ? 0 to 400 khz clock frequency ? esd protection exceeds 2000 v hbm per jesd22-a114, 200 v mm per jesd22-a115 and 1000 v cdm per jesd22-c101 ? latch-up testing is done to jesdec standard jesd78 which exceeds 100 ma ? six packages offered: dip16, so16, ssop16, ssop20, tssop16, and hvqfn16 description the pca9554 and pca9554a are 16-pin cmos devices that provide 8 bits of general purpose parallel input/output (gpio) expansion for i 2 c/smbus applications and were developed to enhance the philips family of i c i/o expanders. the improvements include higher drive capability, 5v i/o tolerance, lower supply current, individual i/o configuration, 400 khz clock frequency, and smaller packaging. i/o expanders provide a simple solution when additional i/o is needed for acpi power switches, sensors, pushbuttons, leds, fans, etc. the pca9554/54a consist of an 8-bit configuration register (input or output selection); 8-bit input register, 8-bit output register and an 8-bit polarity inversion register (active-high or active-low operation). the system master can enable the i/os as either inputs or outputs by writing to the i/o configuration bits. the data for each input or output is kept in the corresponding input or output register. the polarity of the read register can be inverted with the polarity inversion register. all registers can be read by the system master. although pin to pin and i 2 c address compatible with the pcf8574 series, software changes are required due to the enhancements and are discussed in application note an469 . the pca9554/54a open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. the power-on reset sets the registers to their default values and initializes the device state machine. three hardware pins (a0, a1, a2) vary the fixed i 2 c address and allow up to eight devices to share the same i 2 c/smbus. the pca9554a is identical to the pca9554 except that the fixed i 2 c address is different allowing up to sixteen of these devices (eight of each) on the same i 2 c/smbus. ordering information packages temperature range order code topside mark drawing number 16-pin plastic dip 40 c to +85 c pca9554n pca9554n sot38-1 16-pin plastic so (wide) 40 c to +85 c pca9554d pca9554d sot162-1 16-pin plastic ssop 40 c to +85 c pca9554db 9554db sot338-1 20-pin plastic ssop 40 c to +85 c pca9554ts pca9554 sot266-1 16-pin plastic tssop 40 c to +85 c pca9554pw 9554dh sot403-1 16-pin plastic hvqfn 40 c to +85 c pca9554bs 9554 sot629-1 16-pin plastic dip 40 c to +85 c pca9554an pca9554an sot38-1 16-pin plastic so (wide) 40 c to +85 c pca9554ad pca9554ad sot162-1 16-pin plastic ssop 40 c to +85 c PCA9554ADB 9554a sot338-1 20-pin plastic ssop 40 c to +85 c pca9554ats pa9554a sot266-1 16-pin plastic tssop 40 c to +85 c pca9554apw 9554adh sot403-1 16-pin plastic hvqfn 40 c to +85 c pca9554abs 554a sot629-1 standard packing quantities and other packaging data are available at www.philipslogic.com/packaging. i 2 c is a trademark of philips semiconductors corporation. smbus as specified by the smart battery system implementers forum is a derivative of the philips i 2 c patent.
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 3 pin configuration e 16-pin dip, so, ssop, tssop 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 su01410 a0 a1 a2 i/o0 i/o1 i/o2 i/o3 v ss v dd sda scl int i/o7 i/o6 i/o5 i/o4 figure 1. pin configuration e 16-pin dip, so, ssop, tssop pin configuration e 20-pin ssop 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18 19 20 int scl n.c. sda v dd a0 a1 n.c. a2 i/o0 i/o7 i/o6 n.c. i/o5 i/o4 v ss i/o3 i/o2 n.c. i/o1 10 sw02269 figure 1. pin configuration e 20-pin ssop pin configuration e hvqfn 12 11 10 9 5 6 7 8 1 2 3 4 16 15 14 13 su01670 top view a2 i/o0 i/o1 i/o2 i/o3 i/o4 v ss i/o5 int i/o6 i/o7 sda v dd a0 a1 scl figure 2. pin configuration e hvqfn pin description dip16, so16, ssop16, tssop16 pin number hvqfn16 pin number ssop20 pin number symbol function 1 15 6 a0 address input 0 2 16 7 a1 address input 1 3 1 9 a2 address input 2 47 25 1012, 14 i/o0 to i/o3 i/o0 to i/o3 8 6 15 v ss supply ground 9 710 16, 17, 19, 20 i/o4 to i/o7 i/o4 to i/o7 13 11 1 int interrupt output (open drain) 14 12 2 scl serial clock line 15 13 4 sda serial data line 16 14 5 v dd supply voltage 3, 8, 13, 18 n.c. not connected
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 4 block diagram power-on reset input filter i 2 c/smbus control input/ output ports write pulse read pulse a0 a1 a2 scl sda v dd v ss 8-bit i/o0 i/o1 i/o2 i/o3 i/o4 i/o5 i/o6 i/o7 su01411 note: all i/os are set to inputs at reset v cc int lp filter figure 3. block diagram
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 5 registers command byte command protocol function 0 read byte input port register 1 read/write byte output port register 2 read/write byte polarity inversion register 3 read/write byte configuration register the command byte is the first byte to follow the address byte during a write transmission. it is used as a pointer to determine which of the following registers will be written or read. register 0 input port register bit i7 i6 i5 i4 i3 i2 i1 i0 default x x x x x x x x this register is a read only port. it reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by register 3. writes to this register have no effect. the default value `x' is determined by the externally applied logic level, normally `1' when no external signal externally applied because of the internal pull-up resistors. register 1 output port register bit o7 o6 o5 o4 o3 o2 o1 o0 default 1 1 1 1 1 1 1 1 this register reflects the outgoing logic levels of the pins defined as outputs by register 3. bit values in this register have no effect on pins defined as inputs. reads from this register return the value that is in the flip-flop controlling the output selection, not the actual pin value. register 2 polarity inversion register bit n7 n6 n5 n4 n3 n2 n1 n0 default 0 0 0 0 0 0 0 0 this register allows the user to invert the polarity of the input port register data. if a bit in this register is set (written with `1'), the corresponding input port data is inverted. if a bit in this register is cleared (written with a `0'), the input port data polarity is retained. register 3 configuration register bit c7 c6 c5 c4 c3 c2 c1 c0 default 1 1 1 1 1 1 1 1 this register configures the directions of the i/o pins. if a bit in this register is set, the corresponding port pin is enabled as an input with high-impedance output driver. if a bit in this register is cleared, the corresponding port pin is enabled as an output. at reset, the i/os are configured as inputs with a weak pull-up to v dd . power-on reset when power is applied to v dd , an internal power-on reset holds the pca9554 in a reset condition until v dd has reached v por . at that point, the reset condition is released and the pca9554 registers and state machine will initialize to their default states. thereafter, v dd must be lowered below 0.2 v to reset the device. for a power reset cycle, v dd must be lowered below 0.2 v and then restored to the operating voltage. interrupt output the open-drain interrupt output is activated when one of the port pins change state and the pin is configured as an input. the interrupt is deactivated when the input returns to its previous state or the input port register is read. note that changing an i/o from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the input port register.
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 6 simplified schematic of i/o0 to i/o7 write pulse data from shift register v dd i/o0 to i/o7 v ss write configuration pulse d c k ff q d c k q ff d c k q ff d c k q ff input port register polarity inversion register output port register data from shift register data from shift register write polarity pulse configuration register output port register data input port register data polarity register data read pulse su01472 q q q q to int 100 k w q1 q2 note: at power-on reset, all registers return to default values. figure 4. simplified schematic of i/o0 to i/o7 i/o port when an i/o is configured as an input, fets q1 and q2 are off, creating a high-impedance input with a weak pull-up (100 k w typ.) to v dd . the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is configured as an output, then either q1 or q2 is enabled, depending on the state of the output port register. care should be exercised if an external voltage is applied to an i/o configured as an output because of the low impedance paths that exist between the pin and either v dd or v ss .
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 7 device address 01 0 0a2a1a0 slave address su01669 fixed hardware selectable r/w figure 5. pca9554 address 01 1 1a2a1a0 slave address su01418 fixed programmable r/w figure 6. pca9554a address bus transactions data is transmitted to the pca9554/pca9554a registers using the write mode as shown in figures 7 and 8. data is read from the pca9554/pca9554a registers using the read mode as shown in figures 9 and 10. these devices do not implement an auto-increment f unction so once a command byte has been sent, the register which was addressed will continue to be accessed by reads until a new comman d byte has been sent. 12 scl write to port data out from port 345678 sda s0a a a 0 1 0 0 a2 a1 a0 data 1 slave address data to port start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave t pv data 1 valid su01421 9 1 000000 0 command byte p figure 7. write to output port register 12 scl 345678 sda s0a a a 0 1 0 0 a2 a1 a0 data slave address data to register start condition r/w acknowledge from slave acknowledge from slave acknowledge from slave su01422 9 0000001 command byte 1/0 data to register p figure 8. write to configuration or polarity inversion registers
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 8 0 0 a2 a1 a0 0 1 0 0 a2 a1 a0 0 1 s0a a a command byte acknowledge from slave r/w acknowledge from slave a p na acknowledge from slave acknowledge from master s data data r/w first byte at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter last byte su01424 no acknowledge from master 1 slave address data from register data from register slave address figure 9. read from register 01 0 0a2a1a0 read from port data into port sda s1a a data 1 data 4 slave address data from port data from port start condition r/w acknowledge from slave acknowledge from master stop condition t ps data 4 data 2 p data 3 t ph su01465 no acknowledge from master na int t ir t iv 12 scl 345 6 78 9 notes: 1. this figure assumes the command byte has previously been programmed with 00h. 2. transfer of data can be stopped at any moment by a stop condition. figure 10. read input port register
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 9 typical application sw2288 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 v dd v dd scl sda int reset master controller gnd pca9554/ pca9554a a2 a1 a0 v ss v dd subsystem 3 (e.g. alarm system) subsystem 2 (e.g. counter) int v dd alarm controlled switch (e.g. cbt device) enable 10 k w 10 k w 10 k w 2 k w note: device address configured as 0100100 for this example i/o 0 , i/o 1 , i/o 2 , configured as outputs i/o 3 , i/o 4 , i/o 5 , configured as inputs i/o 06 , i/o 7 , are not used and have to be configured as outputs a b 10 k w int (5 v) figure 11. typcial application.
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 10 absolute maximum ratings in accordance with the absolute maximum rating system (iec 134) symbol parameter conditions min max unit v dd supply voltage 0.5 6.0 v i i dc input current e 20 ma v i/o dc voltage on an i/o v ss 0.5 5.5 v i i/o dc output current on an i/o e 50 ma i dd supply current e 85 ma i ss supply current e 100 ma p tot total power dissipation e 200 mw t stg storage temperature range 65 +150 c t amb operating ambient temperature 40 +85 c
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 11 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirab le to take precautions appropriate to handling mos devices. advice can be found in data handbook ic24 under o handling mos devices o. dc characteristics v dd = 2.3 v to 5.5 v; v ss = 0 v; t amb = 40 c to +85 c; unless otherwise specified. symbol parameter conditions min typ max unit supplies v dd supply voltage 2.3 e 5.5 v i dd supply current operating mode; v dd = 5.5 v; no load; f scl = 100 khz e 104 175 m a i stbl standby current standby mode; v dd = 5.5 v; no load; v i = v ss ; f scl = 0 khz; i/o = inputs e 550 700 m a i stbh standby current standby mode; v dd = 5.5 v; no load; v i = v dd ; f scl = 0 khz; i/o = inputs e 0.25 1 m a v por power-on reset voltage (note 1) no load; v i = v dd or v ss e 1.5 1.65 v input scl; input/output sda v il low level input voltage 0.5 e 0.3v dd v v ih high level input voltage 0.7v dd e 5.5 v i ol low level output current v ol = 0.4 v 3 e e ma i l leakage current v i = v dd = v ss 1 e +1 m a c i input capacitance v i = v ss e 6 10 pf i/os v il low level input voltage 0.5 e 0.8 v v ih high level input voltage 2.0 e 5.5 v v ol = 0.5 v; v dd = 2.3 v; note 2 8 10 e ma v ol = 0.7 v; v dd = 2.3 v; note 2 10 13 e ma i o low level out p ut current v ol = 0.5 v; v dd = 4.5 v; note 2 8 17 e ma i ol low le v el o u tp u t c u rrent v ol = 0.7 v; v dd = 4.5 v; note 2 10 24 e ma v ol = 0.5 v; v dd = 3.0 v; note 2 8 14 e ma v ol = 0.7 v; v dd = 3.0 v; note 2 10 19 e ma i oh = 8 ma; v dd = 2.3 v; note 3 1.8 e e v i oh = 10 ma; v dd = 2.3 v; note 3 1.7 e e v v o high level out p ut voltage i oh = 8 ma; v dd = 3.0 v; note 3 2.6 e e v v oh high le v el o u tp u t v oltage i oh = 10 ma; v dd = 3.0 v; note 3 2.5 e e v i oh = 8 ma; v dd = 4.75 v; note 3 4.1 e e v i oh = 10 ma; v dd = 4.75 v; note 3 4.0 e e v i ih input leakage current v dd = 3.6 v; v i = v dd e e 1 m a i il input leakage current v dd = 5.5 v; v i = v ss e e 100 m a c i input capacitance e 3.7 5 pf c o output capacitance e 3.7 5 pf interrupt int i ol low level output current v ol = 0.4 v 3 e e ma select inputs a0, a1, a2 v il low level input voltage 0.5 e 0.8 v v ih high level input voltage 2.0 e 5.5 v i li input leakage current 1 e 1 m a notes: 1. v dd must be lowered to 0.2 v in order to reset part. 2. each i/o must be externally limited to a maximum of 25 ma and the device must be limited to a maximum current of 100 ma. 3. the total current sourced by all i/os must be limited to 85 ma.
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 12 sda scl su01469 t hd;sta t f s t low t r t hd;dat t su;dat t high t f t su;sta s r t hd;sta t sp t su;std p t r t buf s figure 12. definition of timing ac specifications symbol parameter standard mode i 2 c-bus fast mode i 2 c-bus units min max min max f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start conditions 4.7 e 1.3 e m s t hd;sta hold time after (repeated) start condition 4.0 e 0.6 e m s t su;sta repeated start condition setup time 4.7 e 0.6 e m s t su;sto setup time for stop condition 4.0 e 0.6 e m s t hd;dat data in hold time 0 e 0 e ns t vd;ack valid time for ack condition 2 0.3 3.45 0.1 0.9 m s t vd;dat data out valid time 3 300 e 50 e ns t su;dat data setup time 250 e 100 e ns t low clock low period 4.7 e 1.3 e m s t high clock high period 4.0 e 0.6 e m s t f clock/data fall time e 300 20 + 0.1 c b 1 300 ns t r clock/data rise time e 1000 20 + 0.1 c b 1 300 ns t sp pulse width of spikes that must be suppressed by the input filters e 50 e 50 ns port timing t pv output data valid e 200 e 200 ns t ps input data setup time 100 e 100 e ns t ph input data hold time 1 e 1 e m s interrupt timing t iv interrupt valid e 4 e 4 m s t ir interrupt reset e 4 e 4 m s notes: 1. c b = total capacitance of one bus line in pf. 2. t vd;ack = time for acknowledgement signal from scl low to sda (out) low. 3. t vd;dat = minimum time for sda data out to be valid following scl low.
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 13 dip16: plastic dual in-line package; 16 leads (300 mil); long body sot38-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 14 so16: plastic small outline package; 16 leads; body width 7.5 mm sot162-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 15 ssop16: plastic shrink small outline package; 16 leads; body width 5.3 mm sot338-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 16 ssop20: plastic shrink small outline package; 20 leads; body width 4.4 mm sot266-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 17 tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 18 hvqfn16: plastic thermal enhanced very thin quad flat package; no leads; 16 terminals; body 4 x 4 x 0.85 mm sot629-1
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 19 revision history rev date description _6 20040930 product data (9397 750 13289). supersedes data of 2002 jul 26 (9397 750 10163). modifications: ? add dip16 and ssop20 packages to features, ordering information, pin configuration, pin description, and package outline drawings. ? section aregister 0einput port registero on page 4: change default values to `xxxxxxxx' and add second paragraph. ? apower-on reseto section on page 5 modified. ? add new atypical applicationo section on page 9. ? dc characteristics table on page 11: add (new) note 1, and its reference at v por . note 2 re-written. _5 20020726 product data (9397 750 10163). ecn 853-2243 28672 of 26 july 2002. supersedes data of 2002 may 13 (9397 750 09817). _4 20020513 product specification (9397 750 09817) _3 product specification (9397 750 08342) _2 product specification (9397 750 08209) _1 product specification (9397 750 08159)
philips semiconductors product data sheet pca9554/pca9554a 8-bit i 2 c and smbus i/o port with interrupt 2004 sep 30 20 purchase of philips i 2 c components conveys a license under the philips' i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specifications defined by philips. this specification can be ordered using the code 9398 393 40011. definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed i nformation see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the l imiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any o ther conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affec t device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors ma ke no representation or warranty that such applications will be suitable for the specified use without further testing or modificatio n. disclaimers life support e these products are not designed for use in life support appliances, devices, or systems where malfunction of these products ca n reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applica tions do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes in the productseincluding circuits, standard cells, and/or softwaree described or contained herein in order to improve design and/or performance. when the product is in full production (status `production') , relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for th e use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranti es that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . ? koninklijke philips electronics n.v. 2004 all rights reserved. published in the u.s.a. date of release: 09-04 document number: 9397 750 13289

data sheet status [1] objective data sheet preliminary data sheet product data sheet product status [2] [3] development qualification production definitions this data sheet contains data from the objective specification for product development. philips semiconductors reserves the right to change the specification in any manner without notice. this data sheet contains data from the preliminary specification. supplementary data will be published at a later date. philips semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. this data sheet contains data from the product specification. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change notification (cpcn). data sheet status [1] please consult the most recently issued data sheet before initiating or completing a design. [2] the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the l atest information is available on the internet at url http://www.semiconductors.philips.com. [3] for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level i ii iii

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